The present invention relates to semiconductor devices. More specifically, the present invention relates to high-voltage semiconductor devices and low-voltage semiconductor devices sharing a substrate.
Semiconductor process technologies often require a trade-off between density and operating voltages. Circuit elements designed for use at lower voltages (low-voltage elements) can be made smaller and closer together than high-voltage elements. Consequently, low-voltage circuits can be made denser than high-voltage circuits. As a chip""s process heretofore determined whether all of the circuitry on the chip was low-voltage or high-voltage, complex analog digital circuits requiring both high-voltage circuitry and low-voltage circuitry were typically divided among two or more chips.
For example, a circuit might require several high-voltage elements for interface circuitry, while low-voltage elements are acceptable for core logic circuitry. Assuming that a high-voltage chip and a low voltage chip are used, interconnections between the chips, typically provided by signal lines on a printed circuit (PC) board onto which the two chips are mounted, connect the high-voltage circuitry and the low-voltage circuitry. With this approach, chip area may be efficiently used at the cost of complicating the circuit assembly process and increasing the size of the PC board. Furthermore, circuit performance will likely be degraded due to the parasitic capacitance of the wiring between the chips.
Several single chip solutions to the above problems have been proposed to combine high-voltage circuits and low-voltage circuits onto a single chip. One such approach is used by International Rectifier to produce a xe2x80x9cre-entrant surface fieldxe2x80x9d (RESURF) circuit. In a RESURF circuit having a thin epitaxial (epi) layer, the depletion layer can reach the surface, and thereby limit the electric fields in the device. One such circuit is found in the International Rectifier 2110 chip (IGBT gate driver) that uses low voltage components and a few high voltage components. In this and similar applications, the low voltage circuit density suffers due to the high resistivity of the epi layer necessary to make the high voltage devices. The RESURF principle improves this problem somewhat, since the epi layer is relatively thin and can be more heavily doped to provide lower resistivity than it would be without RESURF.
Another problem with a chip that has high voltage devices and low voltage devices is crossover. The crossover problem occurs when high voltage signals are routed across a device, thereby producing large electric fields that may cause the device to breakdown. The following description and accompanying figures demonstrate the problems created by crossover.
FIG. 1A shows a top view of a portion of a typical semiconductor 100 that includes a number of devices, for example, device 102 and device 104. Devices 102 and 104 may be transistor devices or other semiconductor devices. The devices are separated by an isolation diffusion region 106, which is typically a p-type region.
FIG. 1B shows an enlarged top view of the devices 102 and 104 surrounded by the isolation diffusion (iso) region 106. The device 102 includes an n-type epitaxial (epi) region 108, a p-type base region 110, a first n+ region 112 and a second n+ region 114. The device 102 also includes a metal line 116 which is coupled to the second n+ region 114 at point C. If device 102 were a transistor, the base region 110 could be a transistor base, the first n+ region 112 could be an emitter and the second n+ region 114 could be a collector. Additional metal lines may be coupled to the base 110 and emitter 112 at points B and E, respectively.
FIG. 1C shows a cross-sectional view 120 of the device 102 taken at a location indicated by line 130. The cross-sectional view 120 shows semiconductor layers that make up the device 102. From the cross-sectional view 120 is it possible to see that the device 102 includes a p-type substrate layer 122 and a p+ type bottom isolation diffusion region 124. Also visible in the cross-sectional view 120 is an oxide layer 126 that isolates the metal line 116 from the surface of the semiconductor.
The problem of crossover can be seen in FIG. 1C. For example, when high voltages are present on the metal line 116, high electric fields are generated that can cause the device 102 to break down near the junction of the epi 108 and iso region 106 indicated at location 128.
FIGS. 2A and 2B show one technique that has been used to try to solve the crossover problem. FIG. 2A shows an enlarged top view of a region of device 102 that includes the metal line 116 as depicted in FIG. 1B. The region 128 shows where breakdown can occur when high voltages are present on the metal line 116 which crosses over the iso region 106 surrounding the device 102.
FIG. 2B shows the enlarged top view of FIG. 2A and includes poly regions used to try to prevent breakdown due to high voltage on the crossing metal line 116. A series of poly regions are inserted between the metal line 116 and the semiconductor epi region 108. The poly regions include poly1 regions shown at 202, 204 and 206. The poly regions also include poly 2 regions shown at 208 and 210. The poly1 and poly2 regions are positioned in the third dimension such that they are able to be overlapped. The poly regions are shown having different sizes to distinguish between poly1 and poly2 regions. In practice the poly1 and poly2 regions may be the same or different sizes.
FIG. 3 shows an enlarged cross-sectional view of the semiconductor device 102 taken at a location indicated by line 220. In the cross-sectional view, a depth dimension of the overlapping poly1 and poly2 regions is visible. The poly regions are separated by oxide layers shown at 302. The poly1 region 202 is coupled to the collector 114 by electrode 304 and the poly1 region 206 is couple to the isolation region 106 by the electrode 306.
The poly regions form a crossover of connections from the electrode 304 to the electrode 306 in a process referred to as a double poly process. In the double poly process, a capacitive voltage divider is formed utilizing the overlap of the poly1 and poly2 materials as a series of capacitors as shown at 309. For example, the overlap of the poly1204/oxide/poly2210 materials, as shown at 310, forms one of the capacitors. The voltage divider effect of the overlapping poly materials helps to prevent large fields from being generated by the high voltage on the metal line 116, and thus, causing device breakdown at the region indicated by 128.
While this method works for signals with short periods, it becomes unreliable for long duration signals or at high temperatures where oxide conduction will modify the voltage on the individual plates of the capacitors. This occurs because the oxide is not a perfect insulator and it conducts slightly. Conduction in the oxide is dependent on its composition (it is not a pure silicon dioxide) and the environmental conditions (moisture). However slight this conduction may be, eventually (after some time in DC conditions) the voltages at the capacitors will be determined by the oxide conduction. The oxide may be thought of as a resistor having a very high resistance value. As a result of oxide conduction, large voltages may appear at one or more of the capacitors and thereby cause large electric fields which may result in device breakdown.
The present invention includes a method and apparatus for increasing device breakdown voltage and thereby allowing fabrication of high voltage and low voltage circuitry on a single chip.
In one embodiment of the present invention, a semiconductor device is provided. The semiconductor device is constructed within an epitaxial tub of a first conductivity type formed within a dielectric material and comprises a surface diffusion region of a second conductivity type, opposite that of the first conductivity type, extending into the epitaxial tub, a trench surrounding and electrically isolating the epitaxial tub, a metal line coupled to the surface diffusion traversing the semiconductor device and the trench, a first field limiting diffusion region of the second conductivity type disposed between the surface diffusion region and the trench and below the metal line, a poly field plate positioned over the trench and beneath the metal line, and a first contact coupled to the field limiting diffusion region, the first contact extending below the metal line and overlapping the poly field plate.
The semiconductor device may also comprise a second field limiting diffusion region in the epitaxial tub disposed between the surface diffusion region and the first field limiting diffusion region and below the metallization line, and a second contact coupled to the second field limiting diffusion region, the second contact extending to a region below the metallization line in close proximity to the first contact.
In yet another embodiment of the present invention, a method of increasing a breakdown voltage of a semicondcutor device is provided. The semiconductor device is surrounded by a polysilicon-filled trench and includes a surface diffusion region extending into an epitaxial tub. Also included is a metallization line coupled to the surface diffusion region and traversing the semiconductor device and the polysilicon-filled trench. The method comprises the steps of inserting a poly field plate over the polysilicon-filled trench and beneath the metallization line, inserting a first field limiting diffusion region in the epitaxial tub between the surface diffusion region and the polysilicon-filled trench and below the metallization line, and coupling a first contact to the field limiting diffusion region, the first contact extending to a region below the metallization line and overlapping the poly field plate.
A further understanding of the nature and the advantages of the inventions disclosed herein may be realized by reference to the remaining portions of the specification and the attached drawings.